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Os Seminários PESC têm como objetivo trazer palestras acessíveis a um público mais amplo, ministradas por pesquisadores e professores mais experientes (tanto do PESC como de instituições externas). Ao longo do ano, teremos temas e focos variados, podendo ser mais específicos ou mais abrangentes.
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 Sandip Kundu, Full Professor, University of Massachusetts (UMass), EUA16 de março Resumo - Slides Asymmetric multi-core processors (AMPs) comprise of cores with different sizes of micro- architectural resources yielding very different performance and energy characteristics. Since the computational demands of workloads vary from one task to the other, AMPs often provide greater power efficiency than symmetric multicores. Furthermore, as the computational demands of a task change during its course of execution, reassigning the task from one core to another, where it can run more efficiently can further improve the overall energy efficiency. However, too frequent re-assignments of tasks to cores may result in high overhead. To greatly reduce this overhead we propose a morphable core architecture that dynamically adapts its resource sizes and operating frequency to assume one of four possible core configurations. Such a morphable architecture allows more frequent task to core configuration re-assignments for a better match between the current needs of the task and the available resources. To make the online morphing decisions we have developed a runtime analysis scheme using hardware performance counters. Our results indicate that the proposed morphable architecture controlled by the runtime management scheme can improve the performance/watt of applications by 43% over executing on a static AMP. Biografia resumida Sandip Kundu is a Professor at the University of Massachusetts at Amherst. Prior to joining academia, he spent several years in industry: first as a Research Staff Member at IBM Research Division and then at Intel Corporation as a Principal Engineer. He has published well-over 200 research papers in VLSI design and test and holds several key patents including ultra-drowsy sleep mode in processors, and has given more than a dozen tutorials at various conferences. He is a Fellow of the IEEE, Fellow of the Japan Society for Promotion of Science (JSPS), Senior International Scientist of the Chinese Academy of Sciences and a Distinguished Visitor of the IEEE Computer Society. He is currently an Associate Editor of the IEEE Transactions on Dependable and Secure Computing. Previously, he has served as an Associate Editor of the IEEE Transactions on Computers, IEEE Transactions on VLSI Systems and ACM Transactions on Design Automation of Electronic Systems. He has been Technical Program Chair/General Chair of multiple conferences including ICCD, ATS, ISVLSI, DFTS and VLSI Design Conference.
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